In memory ICs, such as random access memories (RAMs), the data in the memory array are accessed by an external data path by means of a number of electrically conducting lines. The electrically conducting lines in the array are conventionally arranged in the form of an array of parallel metallization strips. For example, a dynamic RAM (DRAM) contains an array of hundreds of parallel sense lines (e.g., digit lines). A DRAM also contains an array of parallel access lines (e.g., word lines). The access lines, typically lie at a different planar level than the sense lines. The array of sense lines and the array of access lines lie perpendicular to each other, forming a grid. Memory cells in the DRAM lie at an intersection of an access line and a sense line.
The sense lines in a DRAM can give rise to electrical cross-coupling or “cross-talk.” For example, access to any given sense line may spuriously influence memory cells connected to adjacent sense lines. The term “pattern sensitivity” is applied to this undesirable phenomenon. The problems of cross-talk and pattern sensitivity can arise in other interconnection arrays, such as address busses and data busses where similarly paired, parallel disposed line conductors are employed. In these environments, cross-talk and pattern sensitivity can result in undesirable errors.
Some memories include a twisted sense line architecture having sense lines that are “twisted” to reduce the negative effects of electrical cross-talk and pattern sensitivity. Conventional twisted sense line architectures have a number of disadvantages. One disadvantage is the relatively large amount of chip “real estate” that is typically used by twist junctions where the sense lines are twisted. Yet another disadvantage is that the use of the conventional twisted sense line architecture may result in an inefficient use of the memory cell array space. The conventional twisted sense line architecture does not use space efficiently because it may provide a lower packing density of memory cells than other sense line architecture.
There is a need for a new array architecture including twisted sense lines that may avoid the negative effects of conventional twisted sense line architectures.